The present invention relates to electronic design automation (EDA), and more particularly, to a method and system for validating and fixing conflicts using stitching in the mask layout of a triple-patterning technology.
Improvements in semiconductor integration densities have largely been achieved through corresponding improvements in semiconductor manufacturing technologies. As semiconductor manufacturing technologies move into the deep submicron era, the semiconductor industry is considering a number of new technologies, such as extreme ultraviolet (EUV) lithography and massively parallel electron beam lithography. Unfortunately, these technologies are not ready for production as yet.
Improvements in process technology can increase integration densities beyond what is achievable in present generation photolithography printing. As an example, double-patterning technology has been used for manufacturing design intents having higher pattern density than those pattern densities limited by what is directly printable by photolithography using a given generation manufacturing process with a single mask pattern. Double-patterning technology uses two different masks to produce higher pattern density in a design intent than is achievable by using just one mask. However, double-patterning technology is not able to handle design intents with more complex and higher pattern density, such as at the 10 nm or smaller technology node, that need to be printed using triple or higher multiple-patterning technology. However, triple or higher multiple-patterning technology poses difficulties with design intent validation.
Accordingly, there is a need to validate design intents using triple or higher multiple-patterning technology.